In view of the rapid developments being made in computer technology, there is a demand for ever faster and denser storage media. Among semiconductor memories, a distinction is drawn between different concepts. In the case of dynamic RAMs (Dynamic Random Access Memories), the information is stored in a storage capacitor, but this capacitor loses its charge over the course of time and therefore has to be regularly refreshed. Although DRAM memories have sufficiently fast access times, a stored item of information is lost on disconnection from the voltage source.
By contrast, the memory contents of a static RAM, SRAM (Static Random Access Memory), do not have to be constantly refreshed. However, should the supply voltage fail, the memory contents of a static RAM are lost. Although static RAM memories have short access times, the structure of a static RAM is complex and requires a relatively large number of components. Therefore, the storage densities that can be achieved with static RAMs are too low for some applications.
A non-volatile memory is distinguished by the fact that the information stored in a memory cell of this type is retained for a sufficiently long retention time (a retention time in the range of years is typically required) after a supply voltage has been switched off. A non-volatile semiconductor memory which is often used is the EEPROM (Electrically Erasable and Programmable Read Only Memory).
One important example of an EEPROM is what is known as the floating gate memory. In a floating gate memory which is known from the prior art, an electric charge is stored in a polysilicon structure, the floating gate, which is electrically decoupled from its surroundings. The floating gate is charged and discharged by means of electrical charge carriers which tunnel through a thin insulation layer between the semiconductor and the floating gate. A floating gate memory is programmed by an n+-doped silicon region below the thin insulation layer being brought to a sufficiently high electrical potential, so that the electrical field strength in the thin insulation layer comes close to the breakdown field strength. As a consequence, electrical charge carriers tunnel between the floating gate and the n+-doped silicon region beneath it. As a result, an uncompensated electrical charge remains in the floating gate, where it stays for a sufficiently long retention time even in a state in which electric voltages are no longer being applied to the floating gate memory. In the event of a read operation, the memory transistor, on account of the electrically charged floating gate, has a better electrical conductivity than with an electrically uncharged floating gate, with the information item, which is preferably binary, to be stored being coded in the value for the electrical conductivity of the memory transistor.
However, flash EEPROM cells which are known from the prior art have the drawback that the write and erase times are in the range between approximately one millisecond and approximately ten microseconds. Therefore, the write and erase times of flash memories are considerably slower than the write and erase memories of DRAM memories. By way of example, Widmann, D, Mader, H, Friedrich, H (1996) “Technologie hochintegrierter Schaltungen” [Technology of large scale integrated circuits], Chapter 8.4, Springer Verlag, Berlin, ISBN 3 540 59357 8, provides an overview of the technology of semiconductor memories.
Hitherto, high-density non-volatile memory cells have only been based on silicon. The area taken up by the known non-volatile semiconductor memory cell is in the range from 5 F2 to 8 F2, where F is the minimum feature size in one dimension which can be achieved within a technology generation.
It is known from Fujimaru, K, Matsumura, H (1996) “Theoretical Consideration of a New Nanometer Transistor Using Metal/Insulator Tunnel Junction” Jpn.J.Appl.Phys. Vol. 35, pp. 2090 2094, to form a transistor on a nanometer scale using a metal-insulator tunnel junction. In accordance with the transistor which is known from Fujimaru et al., an electrical metal-insulator-metal tunneling current is controlled by application of an electric voltage to a gate electrode, the gate electrode being arranged above the insulator. According to a computer simulation described in Fujimaru et al., the device described has a similar functionality to a conventional silicon transistor.
Furthermore, Fukushima, K, Sasajima, R, Fujimaru, K, Matsumura, H (1999) “A Novel nanoscale Metal Transistor Fabricated by Conventional Photolithography” Jpn.J.Appl.Phys. Vol. 38, pp. 7233 7236, proposes a realization of a metal transistor in accordance with the theoretical concept described in Fujimaru et al. A fabrication method for forming a metal insulator tunnel transistor (MITT), including a metallic source region and a metallic drain region as well as an electrically insulating channel region, is described using a conventional photolithography process. A gate insulator and a gate electrode are arranged on the electrically insulating channel region arranged between the metallic source region and the metallic drain region. A tunneling current through a tunnel insulator between source and drain regions can be controlled by changing the gate voltage.